This application relies for priority upon Korean Patent Application No. 2001-05976, filed on Feb. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to silicon-on-insulator (SOI) technology, and more particularly to an SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and a method of fabricating the same.
In the semiconductor manufacturing industry, there has been a great deal of attention paid to reducing parasitic capacitance and resistance to increase the operating speed of semiconductor integrated circuits. SOI MOSFETs have been demonstrated to be superior to bulk silicon MOSFETs in terms of low power, high speed very large scale integration (VLSI) applications because of their inherent merits such as less junction capacitance and better device isolation. In addition, there are many advantages in SOI devices such as better immunity to soft errors, reduction in dynamic power, improvement in latch-up resistance even with increased packing density. Despite the above outstanding features of SOI devices. SOI integrated circuits have suffered some lack of commercial success due to technical problems in material processing and device design.
FIG. 1 is a top plan view schematically showing a conventional SOI transistor. Also, FIG. 2 is a cross-sectional view taken along the line I-Ixe2x80x2 of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line II-IIxe2x80x2 of FIG. 1. Referring to FIGS. 1 to 3, an SOI structure includes a supporting substrate 1, a buried insulating layer 3 on the supporting substrate 1 and a semiconductor layer 5 of a first conductivity type on the buried insulating layer 3. The semiconductor layer 5 is etched to form a partial trench region having a depth which is less than the thickness of the semiconductor layer 5. Thus, a semiconductor residue layer exists under the partial trench region. The partial trench region defines a transistor active region 5b and a body contact active region 5a spaced apart from the transistor active region 5b. The partial trench region is then filled with an isolation layer 7. An insulated gate pattern 11 crosses over the transistor active region 5b. The insulated gate pattern 11 is electrically isolated from the transistor active region 5b by a gate dielectric layer 9. Source/drain regions 16 of a second conductivity type are formed at the transistor active region 5b, which is located at both sides of the insulated gate pattern 11. Each of the source/drain regions 16 may have a lightly doped drain (LDD) structure. This LDD structure comprises a lightly doped region 12 and a heavily doped region 15, and may be realized using a spacer 13 formed on the sidewall of the insulated gate pattern 11. Here, the source/drain regions 16 are formed so that they are in contact with the buried insulating layer 3 in order to reduce parasitic capacitance. Impurities of the first conductivity type are implanted into the body contact active region 5a, thereby forming a well contact region 17 at the body contact active region 5a. 
As described above, the conventional SOI technique provides an SOI transistor having an improved characteristic in terms of parasitic junction capacitance. However, sidewall capacitance still exists, since the lower sidewalls of the source/drain regions are in direct contact with the semiconductor residue layer under the isolation layer as shown in FIG. 3. In addition, the semiconductor residue layer completely surrounds the transistor active region 5b. Thus, latch-up immunity is reduced. Accordingly, there continues to be a need for improved SOI techniques.
In view of these problems, there is need for a method and structure for fundamentally eliminating the floating body effect in SOI semiconductor integrated circuits, which is not subject to these limitations.
Accordingly, it is an object of the present invention to provide a technique to eliminate the floating body effect in SOI integrated circuits.
It is another object of the present invention to provide a technique to reduce the parasitic junction capacitance and improve the latch-up immunity in SOI integrated circuits.
Accordingly, the invention is directed to a SOI semiconductor integrated circuit and a method of making the same. The SOI integrated circuit of the invention is formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer. The SOI integrated circuit of the invention includes a plurality of transistor active regions and at least one body contact active region spaced apart from the transistor active regions. The transistor active regions and the body contact active region are composed of a portion of the semiconductor layer. The buried insulating layer, which is located between the transistor active regions and the body contact active region, is covered with a semiconductor residue layer. The semiconductor residue layer is thinner than the transistor active regions and the body contact active region. As a result, a partial trench region exists between the transistor active regions and the body contact active region. The partial trench region is filled with a partial trench isolation layer. An insulated gate pattern crosses over each of the transistor active regions. A full trench isolation layer is interposed between the adjacent transistor active regions. The full trench isolation layer has a bar shape which is parallel with the gate pattern. Also, the full trench isolation layer is in contact with the buried insulating layer between the adjacent transistor active regions.
In one embodiment, the first conductivity type is either P or N type. The semiconductor layer can be a silicon layer.
In one embodiment, the present invention further comprises source/drain regions formed at the transistor active regions, which are located at both side of the insulated gate pattern. The source/drain regions can be of a second conductivity type opposite to the first conductivity type, and the source/drain regions can be in contact with the buried insulating layer. Also, the full trench isolation layer can be in contact with the sidewalls of the source/drain regions, which are parallel with the gate pattern. Thus, the full trench isolation layer isolates SOI MOSFETs formed at the adjacent transistor active regions. As a result, it is possible to minimize the parasitic junction capacitance of the source/drain regions as well as enhance the latch-up immunity.
The invention is also directed to a method of making a SOI semiconductor integrated circuit on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer. In accordance with the method, a predetermined region of the semiconductor layer is etched to form a partial trench region defining a plurality of transistor active regions and at least one body contact active region spaced apart from the transistor active regions. At this time, a semiconductor residue layer, which is thinner than the semiconductor layer, exists under the partial trench region. The semiconductor residue layer is selectively etched until the buried insulating layer is exposed, thereby forming a bar shaped full trench region between the adjacent transistor active regions. As a result of the selective etching, sidewalls of the transistor active regions, which are adjacent to the full trench isolation layer, are exposed. A full trench isolation layer and a partial trench isolation layer are formed in the full trench region and in the partial trench region, respectively. An insulated gate pattern is formed to be across each of the transistor active regions. The gate pattern is formed to be parallel with the full trench isolation layers.
In one embodiment, forming the partial trench region includes forming a first trench mask pattern on the semiconductor layer. Using the first trench mask pattern as an etching mask, the semiconductor layer is etched to a predetermined thickness which is thinner than the semiconductor layer. Forming the first trench mask pattern can include forming a first trench mask layer on the semiconductor layer and patterning the first trench mask layer. The first trench mask layer can be formed by sequentially stacking a pad oxide layer and a pad nitride layer on the semiconductor layer.
Forming the full trench region can include forming a second trench mask pattern having a bar-shaped opening that exposes a portion of the semiconductor residue layer between the adjacent transistor active regions. Using the first and second trench mask patterns as etching masks, the exposed semiconductor residue layer is etched until the buried insulating layer is exposed, and the second trench mask patter is removed. Forming the full trench isolation layer and the partial trench isolation layer can include forming an insulating layer, filling the full trench region and the partial trench region, on an entire surface of the resultant structure where the second trench mask pattern is removed. The insulating layer is planarized until the first trench mask pattern is exposed. The first trench mask pattern is removed to expose the transistor active regions and the body contact active region.
The present invention further comprises forming source/drain regions of a second conductivity type opposite to the first conductivity type at both sides of the insulated gate pattern. The source/drain regions are formed to be in contact with the buried insulating layer. A well contact region can be formed at the body contact active region, the well contact region being doped with impurities of the first conductivity type.